This method generates a general VHDL file for the selected the initial set of components based on inserting multiplexers at the gate inputs of the circuit which helps to perform the simulations in only one session. In this paper, we present an algorithm to improve the testability of digital combinational circuits based on evolutionary approach. Pay attention to the digital circuit testability measures, in addition to can improve the testability of that circuit, can reduce test overhead and testability costs about it. Simulation results show that our proposed method significantly improves the performance factor which represents both circuit area and propagation delay. The simulation results of our proposed method are compared with some conventional and heuristic methods. To evaluate the effectiveness of this method some general benchmark circuits are used in which the circuits with fewer logic cells (minimized space) and lower propagation delay are obtained. Also a multi-objective evaluation mechanism in the form of a weighted cost function is introduced to obtain optimized circuits in case of circuit area and propagation delay. Modification of the algorithm depends on random cell replacement between Imperialist and its colonies as assimilation policy. So a modified version of ICA is proposed to overcome this shortcoming. The Imperialist Competitive Algorithm operates on real values and is not applicable to logic circuits optimization problems. Hence, in order to obtain the accurate results, the blocked rotor test is performed at a frequency 25 % less of the rated frequency.Īlthough, for the induction motors of less than 20kW rating, the effect of the frequency is negligible and hence the blocked rotor test can be performed directly at the rated frequency.This paper proposes a novel evolutionary approach based on modified Imperialist Competitive Algorithm for combinational logic circuits designing and optimization. Thus, the blocked rotor test should be performed at a reduced stator frequency because the effective resistance and the leakage reactance of the rotor at the reduced frequency may differ considerably from their values at the rated frequency.
Under the normal operating conditions, the slip of induction motors is about 2 to 4 percent and the rotor current frequency is from 1 to 2 Hz for the stator frequency of 50 Hz.
The blocked rotor test of the induction motor should be performed under the same conditions of rotor current and frequency that will exist under the normal operating conditions. Therefore, the input power under blocked rotor condition is given by, The voltmeter reads the value of reduced line voltage with blocked rotor (V scl).The ammeter reads the value of line current (I scl) with blocked rotor which is corresponds to the short circuit condition.Therefore, the total input power in the blocked rotor test is equal to the sum of stator copper losses and rotor copper losses for all the 3-phases. Here, a reduced voltage is applied to the stator and rotation of the rotor is not allowed, thus, the core and mechanical losses are negligible. Total input power on short circuit is measured by the two wattmeter method and is given by the algebraic sum of the two watt-meter readings.The readings obtained are given as follows − In the blocked rotor test, a reduced voltage at reduced frequency is applied to the stator of the induction motor through a 3-phase autotransformer so that the rated current flows in the stator winding. In a slip-ring induction motor, the rotor winding is short-circuited through the slip-rings while in a squirrel cage induction motor, the rotor bars are permanently short-circuited with the help of end rings. In the blocked rotor test, the shaft of the motor is locked so that it cannot rotate and the rotor winding is short circuited. The blocked rotor test enables us to determine the efficiency and the circuit parameters of the equivalent circuit of a 3-phase induction motor. The figure shows the circuit diagram for the blocked rotor test of an induction motor.
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